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(R)
HIP5060
t T UC emen ter at OD PR eplacrt Cen /tsc R o om August 1998 ETE il.c OL ded upp BS men ical S inters Om o w. hn Rec Tec or ww No t our IL S tac ER con 8-INT 8 Features 1-8
File Number
3207.2
Power Control IC Single Chip PowerSupply
The HIP5060 is a complete power control IC, incorporating both the high power DMOS transistor, CMOS logic and low level analog circuitry on the same Intelligent Power IC. Both the standard "Boost" and the "SEPIC" (Single-Ended Primary Inductance Converter) power supply topologies are easily implemented with this single control IC. Special power transistor current sensing circuitry is incorporated that minimizes losses due to the monitoring circuitry. Moreover, over-temperature and over-voltage detection circuitry is incorporated within the IC to monitor the chip temperature and the actual power supply output voltage. These circuits can disable the drive to the power transistor to protect both the transistor and, most importantly, the load from over-voltage. As a result of the power DMOS transistor's current and voltage capability (10A and 60V), power supplies with output power capability up to 100 watts are possible.
* * * * * * * * * *
Single Chip Current Mode Control IC 60V, 10A On-Chip DMOS Transistor Thermal Protection Over-Voltage Protection Over-Current Protection 1MHz Operation or External Clock Synchronization Output On-Chip Reference Voltage - 5.1V Output Rise and Fall Times ~ 3ns Designed for 27V to 45V Operation
Applications
* * * * Single Chip Power Supplies Current Mode PWM Applications Distributed Power Supplies Multiple Output Converters
Ordering Information
PART NUMBER HIP5060DY HIP5060DW TEMPERATURE RANGE 0oC to +85oC 0oC to +85oC PACKAGE 37 Pad Chip Wafer
Chip
(1) AGND (6) DGD2 (3) SPST (7) VDDD (8) VDDA (9) V+ (10) SLCT (11) CKIO (12) DGD1 (13) VDDP (14) VDDP S (15) (4) IRFO (2) VINP (5) IRFI S (24) S (23) S (20) S (19) D (25) D (22) D (21) D (18) D (17)
FLTH (37) VREG (36) VCMP (35) PSOK (34) SHRT (33) PSEN (32) TMON (31)
S (28)
S (27)
D (30)
D (29)
NOTE: Unused pads are for trim and test. 153 mils x 165 mils (3.88mm x 4.19mm)
1
D (26)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
S (16)
HIP5060 Simplified Block Diagram
4H 1.1F VIN 0.1F 100F 0.1F VCMP 30.1K FLTN PSOK 0.033F SHRT PSEN TMON DGD1 CKIO SLCT VDDA VDDD IRF1 IRF0 REFERENCE VINP AGND SFST AMP V+ CLOCK AND CONTROL LOGIC GATE DRIVERS S D 4H 0.88F 1 F 4H
DG02
VREG VDDP VDDP 0.1F 0.1F
0.1F
4.02K
0.1F
0.1F
TYPICAL SEPIC CONFIGURATION
2
HIP5060
Absolute Maximum Ratings
DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V Operating Junction Temperature Range . . . . . . . . . .0oC to +110oC Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC
Thermal Information
Thermal Resistance JC (Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3oC/W Max 0.050" Thick Copper Heat Sink) Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110oC (Controlled By Thermal Shutdown Circuit)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = 36V, TJ = 0oC to +110oC; Unless Otherwise Specified
SYMBOL DEVICE PARAMETERS I+ VDDA VINP RVINP Supply Current Internal Regulator Output Voltage Reference Voltage VINP Resistance PSEN = 12V V+ = 15V to 45V, IOUT = 10mA IVINP = 0mA VINP = 0 11.0 5.01 19.5 5.1 900 32 13.2 5.19 mA V V PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIERS |VIO| RIN VREG gm (VREG) gm (SFST) IVCMP IVCMP OVTH CLOCK fq VTH CKIN Internal Clock Frequency External Clock Input Threshold Voltages SLCT = 0V, V DDD = 12V SLCT = 12V 0.9 33 1.0 1.1 66 MHz %VDDD Input Offset Voltage (VREG - VINP) Input Resistance to GND VREG Transconductance IVCMP/(VREG - VINP) SFST Transconductance IVCMP/(VREG - SFST) Maximum Source Current Maximum Sink Current Over-Voltage Threshold IVCMP = 0mA VREG = 5.1V VCMP = 1V to 8V, SFST = 11V VSFST < 4.9V VREG = 4.95V, VCMP = 8V VREG = 5.25V, VCMP = 0.4V Voltage at VREG for FLTN to be latched 15 0.8 -2.5 0.75 6.2 56 30 10 50 6 -0.75 2.5 6.7 mV k mS mS mA mA V
DMOS TRANSISTORS rDS(on) IDSS Drain-Source On-State Resistance Drain-Source Leakage Current I Drain = 5A, TJ = +25oC Drain to Source Voltage = 60V 1 0.13 100 A
CURRENT CONTROLLED PWM |VIO| VCMP VTH IRFO Buffer Offset Voltage (VCMP VIRFO) Voltage at IRFO that disables PWM. This is due to low load current IRFO = 0mA to -5mA, VCMP = 0.2V to 7.6V 100 125 270 mV mV
3
HIP5060
Electrical Specifications V+ = 36V, TJ = 0oC to +110oC; Unless Otherwise Specified (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
CURRENT CONTROLLED PWM (Continued) ITH IRFO Voltage at IRFO to enable SHRT output current. This is due to Regulator Over Current Condition SHRT Output Current, During Over-Current Threshold voltage on SHRT to set FLTN latch IPEAK (DMOSDRAIN)/IIRFI IRFI Resistance to GND Current Comparator Response Time Minimum Controllable Pulse Width Minimum Controllable DMOS Peak Current I (DMOSDRAIN)/t = 1A/ms IIRFI = 2mA I (DMOSDRAIN)/t > 1A/s VIRFO = 8.1V 7.4 8.0 V
ISHRT VTH SHRT IGAIN RIRFI tRS (Note 1) MCPW (Note 1) MCPI (Note 1) START-UP V+ V+ V+ VTH PSEN rPSEN ISFST IPSOK VPSOK VTH SFST
-37 4 3.8 150 25 200
6 30 50 400
-17 8 4.9 360 100 800
A V A/mA ns ns mA
Rising V+ Power-On Reset Voltage Falling V+ Power-Off Set Voltage V+ Power-On Hysteresis Voltage at PSEN to Enable Supply Internal Pull-Up Resistance, to 5.1V Soft-Start Charging Current PSOK High-State Leakage Current PSOK Low-State Voltage PSOK Threshold, Rising V SFST VSFST = 0V to 10V SFST = 0V, PSOK = 12V SFST = 11V, IPSOK = 1mA
22 9 0.8 -1.0 -1 9.4
15 20 -0.7 -
27 12 2.0 -0.4 1 0.4 11
V V V V K A A V V
THERMAL MONITOR TEMP (Note 1) NOTE: 1. Determined by design, not a measured parameter. Substrate Temperature for Thermal Monitor to Trip TMON pin open 105 135
oC
4
HIP5060 Pin Descriptions
PAD NUMBER 1 2 3 4 DESIGNATION AGND VINP SFST IRFO Analog ground. Internal 5.1V reference. Controls the rate of rise of the output voltage. Time is determined by an internal 0.7A current source and an external capacitor. A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current sense comparator. The maximum current is set by the value of the resistor, according to the equation: IPEAK = 32/R. Where R is the value of the external resistor in K and must be greater than 1.5K but less than 10K. For example, if the resistor chosen is 1.8K, the peak current will be 17.8A. This assumes VCMP is 7.3V. Maximum output current should be kept below 20A. See IRFO Ground of the DMOS gate driver. This pad is used for bypassing. Voltage input for the chip's digital circuits. This pad also allows decoupling of this supply. This is the analog supply and internal 12V regulator output. This is the main supply voltage input pad to the regulator IC. Because of the high peak currents this pad must be well bypassed with at least a 0.7F capacitor and may be composed of seven, single 0.1F chip capacitors. This pad provides for the option of using either internal 1MHz operation of for an external clock. Floating or grounding this pad will place the internal clock at the CKIO pad. Returning this terminal to V DDD or 12V will allow application of an external clock to the IC via the CKIO pad. There is an internal 50K pull down Clock output when SLCT is floated or grounded. External clock input when SLCT is returned to 12V. This pad is the return for the digital supply. These pads are used to decouple the high current pulses to the output driver transistors. The capacitor should be at least a 0.1F chip capacitor placed close to this pad and the DMOS source pads. Source pads of the DMOS power transistor. Drain pads of the DMOS power transistor. This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a nominal junction temperature of +125oC. This terminal is provided to activate the converter. This terminal may be left open or returned to 5V for normal operation. When the input is low, the DMOS driver is disabled. 25A is internally applied to this node when there is an over-current condition. This pad provides a delayed positive indication when the supply is enabled. Output of the transconductance amplifier. This node is used for both gain and frequency compensation of the loop. Input to the transconductance error amplifier is available on this pad. The other input is internally connected to the 5.1V reference, VINP, Pad 2. This is an open drain output that remains low when V+ is too low for proper operation. This node and PSEN are useful in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current is experienced. DESCRIPTION
5 6 7 8 9
IRFI DGD2 V DDD VDDA V+
10
SLCT
11 12 13 & 14
CKIO DGD1 VDDP
15, 16, 19, 20, 23, 24, 27, 28 17, 18, 21, 22, 25, 26, 29, 30 31
S D TMON
32 33 34 35 36 37
PSEN SHRT PSOK VCMP VREG FLTN
5
HIP5060 Functional Block Diagram
VDDA
SLCT
CKIO
VDDD
V+
12V REGULATOR 12V REGULATOR VREF VDDP 20K VREF = 5.1V V+ MONITOR + -
VDDA
BIAS CIRCUITS 1MHz CLOCK 50K MULTIPLEXER VDDP VDDP
BAND GAP REFERENCE REGULATOR POWER SUPPLY ENABLE VREF VDDA 0.7A
PSEN
PSOK
POWER SUPPLY OK
360K 140K
DRAIN S FLIP-FLOP R Q FAST RESET GATE DRIVERS
SFST
VREF 900 gm AMP + LOW LOAD + 98K 4K OVER VOLTAGE VREF
VINP
VREG
11.3K
CONTROL AND BLANKING LOGIC
CURRENT MONITORING AMP
SOURCE
FLTN
45K VREF
+
TMON
THERMAL MONITOR + -
SHRT VREF 26K
SHORT - CIRCUIT + 13K
IRF0
VCMP
DGD1
DGD2
AGND
IRFI
6

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